A lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). In such a case, a patterning device (e.g., a mask) may contain or provide a circuit pattern corresponding to an individual layer of the IC (“design layout”), and this circuit pattern can be transferred onto a target portion (e.g. comprising one or more dies) on a substrate (e.g., silicon wafer) that has been coated with a layer of radiation-sensitive material (“resist”), by methods such as irradiating the target portion through the circuit pattern on the patterning device. In general, a single substrate contains a plurality of adjacent target portions to which the circuit pattern is transferred successively by the lithographic apparatus, one target portion at a time. In one type of lithographic apparatuses, the circuit pattern on the entire patterning device is transferred onto one target portion in one go; such an apparatus is commonly referred to as a wafer stepper. In an alternative apparatus, commonly referred to as a step-and-scan apparatus, a projection beam scans over the patterning device in a given reference direction (the “scanning” direction) while synchronously moving the substrate parallel or anti-parallel to this reference direction. Different portions of the circuit pattern on the patterning device are transferred to one target portion progressively. Since, in general, the lithographic apparatus will have a magnification factor M (generally <1), the speed F at which the substrate is moved will be a factor M times that at which the projection beam scans the patterning device.
Prior to transferring the circuit pattern from the patterning device to the substrate, the substrate may undergo various procedures, such as priming, resist coating and a soft bake. After exposure, the substrate may be subjected to other procedures, such as a post-exposure bake (PEB), development, a hard bake and measurement/inspection of the transferred circuit pattern. This array of procedures is used as a basis to make an individual layer of a device, e.g., an IC. The substrate may then undergo various processes such as etching, ion-implantation (doping), metallization, oxidation, chemical-mechanical polishing, etc., all intended to finish off the individual layer of the device. If several layers are required in the device, then the whole procedure, or a variant thereof, is repeated for each layer. Eventually, a device will be present in each target portion on the substrate. These devices are then separated from one another by a technique such as dicing or sawing, whence the individual devices can be mounted on a carrier, connected to pins, etc.
As noted, microlithography is a central step in the manufacturing of ICs, where patterns formed on substrates define functional elements of the ICs, such as microprocessors, memory chips etc. Similar lithographic techniques are also used in the formation of flat panel displays, micro-electro mechanical systems (MEMS) and other devices.
In lithographic processes, it is desirable to frequently make measurements of structures created for process control and verification. One or more parameters of the structures are typically measured or determined, for example, the overlay error between successive layers formed in or on the substrate. However, target selection by frequent measurement is labor-intensive and time-consuming. Therefore, it makes sense to implement a computer-aided design (CAD) system that is capable of automatically generating designs of metrology targets in the simulation domain without the need for actual frequent measurement.
Currently, metrology target designers measure dimensions of patterns formed on a resist layer, and feed that data to a computerized lithography process model to predict the device structure that will be printed on the actual substrate. However, as lithography processes get more complex, the device structure formed on the substrate after processing tend to become significantly different from the patterns formed in the resist. Examples of complex lithography processes include spacer-based double lithography process, FinFET processes etc. Because of the process-induced complexities, it is becoming difficult for metrology target designers to render the correct target structure from measured or modeled resist patterns.
Additionally, some substrate structures (e.g., odd number of fins in a FinFET) are not compatible with the lithography process, but a designer could manually add those problematic structures by mistake. Those structures cannot be generated properly via a CAD tool. Also, without the CAD tool, targets of different designs for every layer or layer pairs have to be drawn one at a time. With the large number of lithography layers and different design options, the manual drawing of all possible targets become unmanageable. Therefore, not only automatic generation of metrology target design is important, but proper organization and easy retrieval of the auto-generated designs are equally important.
Further, it is beneficial to alter target dimensions to test the design robustness with respect to process perturbations. Currently, the dimensional alterations are purely geometrical and may not be process compatible. For example in a FinFET process, some of the fin side wall angles are related and should be altered together. But the current methods cannot handle this special requirement. Therefore, it is desirable to have the capability to design multiple metrology targets in a flexible and time-and-resource-efficient manner in the simulation domain from which a lithographer may select the targets that are optimal for a selected process.